“DACs are ideal building blocks for waveform generation applications. Because the R-2R architecture of multiplying digital-to-analog converters (DACs) is ideal for low noise, low glitch, fast settling applications. When generating waveforms from a fixed reference input voltage, some important AC specifications must be considered, including settling time, mid-scale glitches, and digital SFDR.

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DACs are ideal building blocks for waveform generation applications. Because the R-2R architecture of multiplying digital-to-analog converters (DACs) is ideal for low noise, low glitch, fast settling applications. When generating waveforms from a fixed reference input voltage, some important AC specifications must be considered, including settling time, mid-scale glitches, and digital SFDR.

Today we will analyze these important DAC specifications related to waveform generation.

Build time

Assuming the DAC is driven by a real wideband low impedance signal source (reference voltage and ground pins), it settles quickly. Therefore, the slew rate and settling time of the multiplying DAC are primarily determined by the op amp. Specifications that determine the ac performance of an op amp include its input capacitance (which must be kept to a minimum) and 3 dB small-signal bandwidth. Note that the bandwidth of the op amp is limited because it must drive the large load of the DAC feedback resistor. For example, a feedback resistor of 10 kΩ is a considerable load, and it is the dominant pole that determines the bandwidth of the circuit configuration.

Figure 1. 100 ns Settling Time

mid-level glitch

For the R-2R structure, the main glitch due to code changes occurs when a 1 LSB change occurs around midscale. In a 12-bit system (such as the DAC AD5444), the midscale change is from 7FFH to 800_H or from 800_H Code changes to 7FFH. If the glitch is severe, it may adversely affect motor/valve/actuator control applications. When the multiplying DAC tries to go from 7FFH to 800_H, the MSB of the DAC toggles slower than the other bits. Therefore, in the nanoseconds before the MSB switches to 1, the DAC sees 000_H. This is what the yellow curve in Figure 2 shows; switching at the MSB and pulling the DAC output back to 800_H Before, the output was changing towards 0 V.

Figure 2. Midscale Glitch

Digital SFDR

Spurious Free Dynamic Range (SFDR) refers to the usable dynamic range of a DAC beyond which spurious noise can interfere with or distort the fundamental signal. SFDR measures the difference between the magnitude of the fundamental and the largest harmonic or non-harmonic related spur in the range from DC to the full Nyquist bandwidth (half the DAC sampling rate). Narrowband SFDR measures SFDR over an arbitrary window range. An ideal sine wave has an infinite number of points per cycle. However, digitally generated sine waves are limited by the fixed update rate and DAC resolution. The number of points per cycle is given by:

in:

N = number of sampling points
Clock = update rate of the DAC
f_OUT = output frequency of the resulting waveform

Figure 3 shows a 20 kHz sine wave with an update rate of 1 MHz and 50 samples per cycle using the 12-bit AD5444. The maximum update rate for the AD5444 is 2.7 MSPS. To generate waveforms with more samples, a faster update rate must be used. The AD5445 with the parallel interface provides a maximum update rate of 20 MSPS.

Figure 3. Wideband SFDR, f_OUT = 20 kHz, clock = 1 MHz