“The reduction of switching losses in power devices in power Electronic systems such as motor drives is limited by parameters such as electromagnetic interference (EMI) or switching voltage slope. This problem is usually solved by choosing an effective power Transistor gate resistance. But this cannot be adjusted autonomously during operation. This article will describe a simple way to overcome this challenge by paralleling conventional gate driver chips. Evaluation of characterization data related to turn-on energy improvement improvements is also presented.
Original Wolfgang Frank
The reduction of switching losses in power devices in power electronic systems such as motor drives is limited by parameters such as electromagnetic interference (EMI) or switching voltage slope. This problem is usually solved by choosing an effective power transistor gate resistance. But this cannot be adjusted autonomously during operation. This article will describe a simple way to overcome this challenge by paralleling conventional gate driver chips. Evaluation of characterization data related to turn-on energy improvement improvements is also presented.
There are generally two optimization goals for gate resistance selection of power semiconductors. On the one hand, choosing a gate resistor with a smaller resistance value can make the switching speed of the power semiconductor faster. This will reduce switching losses and thus lower overall losses. On the other hand, choosing a larger gate resistance, such as dvCE/dt or diC/dt, can reduce the switching speed. This reduces ringing that occurs in the gate circuit due to parasitic stray inductance or coupling capacitance. Therefore, the optimal configuration of the gate resistance must be achieved by means of a compromise. However, it is sufficient to manage only specific operating points such as temporary overload or light load conditions. These conditions are switched more slowly than when the application system is operating normally.
Motor drives operating under low load conditions are typically light load conditions. Since the commutation current from the diode is small, the forward current flowing into the IGBT is also small, which may cause severe oscillation when the corresponding IGBT is turned on too fast.If the forward current can reach the nominal current25% or more, these oscillations can be greatly attenuated or even eliminated.
Recommended Gate Drive Concept
A normal gate drive circuit is shown in Figure 1. The turn-on and turn-off currents of a gate driver depend on the gate current of the gate resistor. Current iOUT+ charges the gate of the power transistor and current iOUT- discharges the gate of the power transistor.
Figure 1. Conventional gate driver using a single chip
Figure 2 shows the proposed gate drive concept with improved turn-on current capability. Connect two gate drivers with model number 1EDI60I12AF in parallel. The two IN+ are used in parallel for regular PWM input signals. The terminal IN- of the gate driving chip IC2 is used to select whether the chip IC2 participates in the output together. This signal can be easily generated by application control or controlled by sensing signals related to switching performance, such as self-temperature or collector current. Enabling the IC2 chip can inject another component iOUT+2 to the gate current ig to participate in the turn-on process together.
Figure 2. Proposed Gate Drive Design
As shown in Figure 2, only the driver IC1 can be used for shutdown. Otherwise there may be a situation where IC1 is sourcing current and IC2 is sinking current, which can lead to excessive power losses in the chip or in the associated gate resistors.
The time control of the gate current ig
Figure 3. Gate Current Time Control for IC1 and IC2
Evaluation of measurement results
Figure 4 shows the results of a double-pulse test of the turn-on energy Eon and dvCE/dt of IC for different gate resistances and collector currents under a gate drive concept with improved turn-on current capability. The gate resistance varies from 10Ω to 47Ω (the conventional solution corresponds to the solid line), and the collector current is between 10% and 100% of the nominal current. Calculate dvCE/dt values between 90%/10% by software. The test power transistor is Infineon’s 40A/1200V IGBT (IKW40N120T2).
Figure 4. Effect of the proposed rate control technique on turn-on dvCEon/dt (top) and switching energy Eon (bottom)
The slew rate dvCE/dt increases as the collector current increases. The respective gate resistances of the two gate drivers are Rg1=18Ω and Rg2=47Ω. The gate resistor Rg1 can be used in the smaller collector current range by applying the recommended gate drive technique. Presumably, the green line corresponding to Rg=20Ω in Figure 4 will achieve similar results to Rg=18Ω, but with a smaller dvCE/dt. When the nominal current is above 50% (IC=20A), it will switch to the case of using two gate driver chips to run in parallel (at this time, Rg is the resistance value of Rg1 and Rg2 in parallel, 13Ω).
The turn-on losses are shown in the lower graph in Figure 4. The turn-on loss at nominal current (IC=40A) can be reduced from 4.8mJ to 3.6mJ when using the gate drive recommended in this article. This corresponds to a reduction in turn-on loss Eon of about 25%.
Two gate drivers per power transistor, coupled with separate on/off resistors, can be an easy way to improve power transistor performance. Improvements in turn-on current capability or turn-off current capability can be achieved by using only two gate driver chips. Furthermore, using a gate driver chip such as Infineon’s 1EDI60I12AF also reduces the design effort compared to using a functionally equivalent discrete solution. The benefits of up to 25% lower turn-on energy Eon and improved turn-on current capability can be achieved simply by following general design guidelines. Therefore, the proposed gate drive concept outperforms conventional solutions.
 W. Frank: Real-time adjustable gate current control IC solves dv/ dt problems in electric drives, Proc. PCIM 2014
 Mitsubishi: System Benefits of Using G1 Series Intelligent Power Modules (IPM), Bodo´s Power Magazine, Edition 3, Germany, 2017
 Gambica Association: Motor Insulation Voltage Stresses Under PWM Inverter Operation, Technical report No.1, third edition, UK, 2006.
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