“Phased array radar systems utilize multiple transmit and receive channels for proper operation. Previously, these platforms were constructed using separate transmit and receive integrated circuits (ICs). These systems use separate chips for the digital-to-analog converter (DAC) of the transmit (Tx) circuit and the analog-to-digital converter (ADC) of the receive (Rx) circuit. This distinction makes many systems large, expensive, and power-hungry in order to obtain the required number of channels to perform the required function. These systems also typically take a long time to market due to complex manufacturing and calibration processes.Recently, however, a method has emerged that utilizes integrated transceivers, which

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By Mike Jones, Peter Delos Analog Devices

Summary

Phased array radar systems utilize multiple transmit and receive channels for proper operation. Previously, these platforms were constructed using separate transmit and receive integrated circuits (ICs). These systems use separate chips for the digital-to-analog converter (DAC) of the transmit (Tx) circuit and the analog-to-digital converter (ADC) of the receive (Rx) circuit. This distinction makes many systems large, expensive, and power-hungry in order to obtain the required number of channels to perform the required function. These systems also typically take a long time to market due to complex manufacturing and calibration processes. Recently, however, an approach has emerged that utilizes integrated transceivers, which combine many functions that were once considered disparate into a single IC. These ICs enable small size, low power consumption and low cost, phased array radar systems with high channel count and faster time to market.

Introduction to Integrated Transceivers

Integrated transceivers, such as the one shown in Figure 1, combine multiple functions onto a single IC. For example, new transceivers integrate DACs, ADCs, local oscillator (LO) frequency synthesizers, microprocessors, mixers, and more into a 12 mm × 12 mm single-chip product. In addition, the product integrates two receive channels and two transmit channels, as well as multiple digital signal processing (DSP) components to obtain the instantaneous bandwidth required by the system. An application programming interface (API) is also provided for operating the transceiver on the client platform. Gain and attenuation control can be implemented using an on-chip front-end network. Built-in initialization and tracking calibration routines are used to provide the performance required for many communications and military applications.

Figure 1. The ADRV9009 is an example of an integrated transceiver that integrates multiple functions into a single IC.

These integrated transceivers are able to create all the clock signals required by the transmitter and receiver by injecting a reference clock signal called REF_CLK. All clocks required for DAC/ADC sampling, LO generation, and microprocessor clocking are then synthesized by an on-chip phase-locked loop (PLL). If the internal LO phase noise is not sufficient for the customer’s application needs, the user can choose to inject their own low phase noise external LO.

Data from components is offloaded via the standardized JESD204b multi-gigabit serial data interface. This interface supports simultaneous reception and transmission of large amounts of data. New integrated transceiver solutions can help provide interface IP to help customers accelerate time to market. If deterministic latency and data synchronization are required, users can take advantage of the built-in Multi-Chip Synchronization (MCS) feature and assert the SYS_REF signal as the primary timing reference for the Initial Lane Alignment Sequence (ILAS). 1

In addition, the built-in RFPLL phase synchronization feature can be used to set the LO phase of the transmit or receive channel to be deterministic relative to the primary reference phase. By utilizing the MCS and RFPLL phase synchronization features, phase alignment can be replicated when initializing components, frequency tuning, or switching the radio on and off in software. Figure 2 shows an example of a new integrated transceiver that provides deterministic phase and supports all of these features.

Figure 2. The built-in RFPLL phase synchronization feature provides a deterministic phase relationship between the system and the primary reference source.

Figure 3. Multiple integrated transceivers can be used to increase the channel count of a system.

Use multiple integrated transceivers

If the system requires more than two receivers and two transmitters, the user can still use multiple integrated transceivers and benefit from the small size achieved due to the single-chip receive and transmit channels. An example of this technique is shown in Figure 3. Multiple integrated transceivers can be synchronized by using concurrent SYS_REF pulses to trigger the internal voltage dividers of all ICs simultaneously. These SYS_REF pulses can be issued by a clock chip or a baseband processor with a programmable delay that is responsible for the path length mismatch between ICs. Both data paths and multiple LOs across multiple chips can be deterministic.

Integrated transceivers are the backbone of phased array radar platforms

The increased channel count through the use of synchronous integrated transceivers makes these devices the backbone of phased array radar platforms. When combined with phase- and amplitude-aligned transmit and receive channels, the use of multiple integrated transceivers can demonstrate system-level improvements in dynamic range, spurious, and phase noise.

On-chip DSP features, such as numerically controlled oscillators (NCOs) and digital upconverters, or digital downconverters (DDCs), now support system-level spurious decorrelation methods within a single IC. 2

By combining transceiver channels using multiple integrated transceivers, it was shown that both system-level noise spectral density (NSD) and spurious performance are improved. This move improves the dynamic range of phased array radar systems by reducing the effective noise floor of the system while maintaining the full functionality of the channels. Figure 4 shows system-level measurements after integrating up to eight integrated transceiver receive channels, effectively increasing the number of bits in a phased array system. Note that when increasing from one to eight channels, the NSD and the calculated noise floor (indicated by the red line in the graphs) will increase by 6 dB. This is because, although there are 8 channels in total, among the 4 integrated transceivers used to create these 8 channels, there are only 4 distinct and uncorrelated LOs (that is, NLO = 4).

Therefore, the following improvements are achieved

The obtained results are similar to the experimental results provided by the integrated transceiver. In addition, redundant imaging frequencies are aggregated in an uncorrelated manner, enabling system-level spurious performance improvements. Further improvements in performance are achieved as the number of channels increases, enabling a scalable system.

Figure 4. Integrating the receive channel using the ADRV9009 integrated transceiver reduces noise spectral density and improves dynamic range.

In addition, the phase noise of a phased array system can be improved by aligning the phases and integrating multiple integrated transceiver channels. As can be seen from the measurements shown in the top three curves in Figure 5, the phase noise performance improves after combining 8 channels with the internal LOs of the 4 integrated transceiver ICs. To repeat, with 4 distinct and uncorrelated LOs (that is, NLO = 4), the phase noise increases by 6 dB when going from 1 transmit channel to 8 transmit channels. Increasing the number of channels can further increase the phase noise of a phased array radar system. Alternatively, an external LO can be injected into each sub-array consisting of NTRx integrated transceivers and the initial phase noise can be improved from the sub-array level (as shown by the blue curve in Figure 5). However, in this way, each element in the sub-array will be related to each other because they all share the same LO source, so it cannot provide channel aggregation improvement in the sub-array by itself. For the external LO phase noise data shown in Figure 5, a Rohde & Schwarz SMA100B signal generator was used as the external LO source.

Figure 5. Integrating multiple ADRV9009 transmit channels can improve system-level phase noise performance when using the internal LO.

Injecting an external LO will improve the initial phase noise of the sub-array.

Figure 6. DSP features can now implement digital phase shifting with on-chip NCO and DDC/DUC.

Increasing the number of channels and optimizing the phase shift will allow the integrated transceiver to form a narrower beam.

Integrated DSP features such as NCO, digital phase shifters, and DUC/DDC allow baseband phase shift and frequency shift in the digital domain, allowing digital beam implementation in multi-channel, integrated transceiver-based phased array radar systems forming. By integrating multiple functions onto a single IC, the system can now utilize integrated transceivers for antenna lattice spacing in many relevant phased array applications. Increasing the number of channels with more transceivers generally narrows the beam, but results in a larger system. However, with the integration of multiple functions into a single IC, the rate of system size is still smaller than in the past. After simulating the radiation pattern using MATLAB®, Figure 6 shows how the beam narrows and the theoretical lobe amplitude becomes deeper as the number of channels increases from N = 23 to N = 210. The actual power null will be indicated in the antenna design.in conclusion

Integrating multiple digital and analog functions in a single IC enables smaller phased array radar systems. These systems support the implementation of digital beamforming and hybrid beamforming, depending on the system specification. System-level performance improvements have been demonstrated using the ADRV9009 from Analog Devices. These integrated devices enable many new systems to use the same hardware to run multiple applications.

References

1 Harris, J. What is the JESD204 standard and why should we care about it? Analog Devices Technical Article, MS-2374, 1-4. October 2013.

2 Delos, P., Jones, M., Robertson, M. RF transceivers enable forced spurious decorrelation within digital beamforming phased arrays. Analog Devices technical articles. August 2018.