“ADCs need to have adequate signal acquisition analog interfaces to gain performance. Traditional general-purpose ADC front ends include multiple differential input channels, digitally programmable gain, and track-and-hold functionality. This Design Idea presents a complete new high-performance, low-component-count ADC front-end that implements a complete set of standard functions (Figure 1).

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ADCs need to have adequate signal acquisition analog interfaces to gain performance. Traditional general-purpose ADC front ends include multiple differential input channels, digitally programmable gain, and track-and-hold functionality. This Design Idea presents a complete new high-performance, low-component-count ADC front-end that implements a complete set of standard functions (Figure 1). However, it also comes with a flying capacitor differential input concept and the divergent exponential negative time constant described in an earlier design example (Reference 1). This Design Idea adds multiplexed inputs and a general track-and-hold function to the circuit.

Figure 1: This high-performance, low-component-count ADC front-end implements standard functional groups.

The multiplexer address and hold mode status bits control the acquisition and shaping of the signal. When the hold state is zero and the multiplexer address is equal to the selected input channel, the flying capacitor C1 is connected to the positive and negative differential input terminals for input voltage acquisition. A hold transition to 1 isolates C1 from the input. So the address of the multiplexer is 0, the hold state returns to 0, and the input voltage is exponentially amplified with a negative time constant. From this point, until held again, and the connected ADC is sampling, and the point where the output voltage is converted, both the input voltage and the output voltage are divergent exponential functions of time, with a gain equal to 2 (1+t/10µs).

Figure 2: Only the resolution of the timing during amplification limits the gain setting.

This new circuit builds on an earlier design and has the features required for differential inputs to multiple instruments. Also, neither the resistor matching issue nor the CMR (common mode rejection) of the op amp will limit the CMR of the circuit. Stray capacitance is a contributing factor to CMR, but it can be minimized through careful circuit layout. The circuit also has rail-to-rail inputs and virtually unlimited programmable gain. Furthermore, the resolution of the gain setting is only affected by the timing resolution during amplification (Figures 2 and 3). This circuit also has an output amplitude of ±10V, which is one to three times higher than that of a monolithic digital programmable gain instrumentation amplifier.

Figure 3: This input, output voltage gain plot shows the duration of a track/amplification logic transition.

The inherent noise and dc of the selected op amp, exponential timing generation and repeatability, ADC sampling resolution, and stability of the RC time constant are all major limiting factors for signal processing performance and amplifiers such as their gain setting, DC error, noise, and jitter. In a circuit, a timing error or jitter during amplification of 1 ns is equivalent to a gain setting error of 0.007%.