ALD fill technology for ‘higher’ memory devices

For 3D NAND, DRAM and logic chip manufacturers, gap filling in complex architectures with high aspect ratios has always been a challenge.

In this regard, Aaron Fellis, vice president and general manager of Dielectric Atomic Layer Deposition (ALD) products, Lam Group, introduced how the Striker® FE enhanced ALD platform will advance the technology roadmap with its high performance.

Deposition technology is a key element in advancing the advancement of memory devices. But with the advent of 3D NAND stacks, the limitations of existing fill methods have begun to emerge.

The Striker® FE Enhanced Atomic Layer Deposition (ALD) platform launched last year by Lam Group addresses semiconductor manufacturing challenges in 3D NAND and DRAM. The platform uses an advanced dielectric fill technology called “ICEFill” for 3D NAND and DRAM architectures and logic devices at advanced nodes. Aaron Fellis, vice president and general manager of Dielectric ALD products at Lam Group, pointed out that the need for filling-related technologies has always existed, but those old methods have not been able to meet the new needs, especially as 3D NAND stacks are getting higher and higher. “In addition to stacking very high layers, in order to integrate the different steps, we have to etch to meet different feature requirements,” he said. “Eventually we need to refill with dielectric materials, the most common of which are Silicon oxide.”

ALD fill technology for ‘higher’ memory devices

Fellis pointed out that traditional filling methods used in the semiconductor manufacturing industry, such as chemical vapor deposition, diffusion/furnace and spin-coating processes, always have trade-offs between quality, shrinkage and fill rate, so they can no longer meet the production needs of 3D NAND. “These techniques tend to shrink and cause actual structural deformations of the build and design”.

Silicon oxide is still the material of choice for interstitial filling due to its stability, temperature tolerance and good electrical properties, but its deposition techniques have changed. Take Lam Group’s Striker ICEFill as an example, the solution uses Lam’s unique surface modification technology to achieve highly selective bottom-up seamless filling while maintaining the inherent properties of atomic layer deposition (ALD). film quality.

“Standard ALD technology can greatly improve the film quality after deposition, which solves the problem of shrinkage,” Fellis said.

Striker® FE Enhanced ALD Platform with ICEFill Advanced Dielectric Interstitial Technology for Filling 3D NAND and DRAM Architectures

According to Fellis, even with good internal mechanical integrity achieved with high-density materials, standard ALD can still lead to gaps in some devices, and its ductility can be problematic. The bottom-up ICEFill, on the other hand, achieves very high-quality internal film formation without shrinkage. “It’s very malleable,” he says, which means it can be used to fill any step, including to improve mechanical strength and electrical properties. “In a specific gap inside the fabricated device, the filling Materials all have uniform properties.”

Deposition technology for memory devices has its own roadmap, and the various memory technology advancements that drive it also determine the “shelf life” of existing technologies, Fellis said. “Technology will evolve to higher and smaller.” Anticipating the challenges posed by higher 3D NAND stacks, Lam Group has already started to improve its Striker products. “As customers move on their roadmaps, we see their need to improve film-forming performance,” he said. “Stacking continues to be a driver of innovation.”

Risto Puhakka, president of VLSI Research, a US semiconductor industry research company, said that as a leader in ALD technology, Lam’s technology needs reflect the general needs of the storage industry, that is, to increase storage density to meet the high storage requirements of applications such as artificial intelligence, but At the same time, cost increases must be avoided. With the increasing stack height of storage devices such as 3D NAND, higher requirements are also placed on filling technology. “There are more and more manufacturing challenges related to stacking, and chipmakers are also concerned about the cost of being too expensive,” Puhakka said. In this case, continuing to use very familiar materials such as silicon oxide helps to better Forecast costs.

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